The present invention relates to analog-to-digital converters for large detector arrays. More specifically, the invention relates to parallel "pipeline" analog-to-digital converters which have varying degrees of parallelism throughout the stages of the pipeline.
Many analog-to-digital converter designs are known in the art. They have different characteristics that make them suitable for a variety of applications. ".SIGMA..DELTA." (Sigma Delta) analog digital converters can be made to have high precision (in the range of 16-20 bits), but are typically rather slow. "Flash" type analog-to-digital converters are much faster but having much lower precision, typically in the neighborhood of 6 bits. Various other analog-to-digital converter designs are in commercial use. On balance, the criteria that drive selection of a particular analog-to-digital converter arc power consumption, precision, and speed.
One type of analog-to-digital converter is a pipelined converter. A pipelined analog-to-digital converter digitizes an analog signal in increments over multiple stages. The first stage digitizes the most significant bit or bits and then passes the undigitized residue to the second stage. That stage then digitizes the next most significant bit or bits, generates its own residue and passes it to the next successive stage (if any exist). While the second stage is digitizing its portion of the analog signal, the first stage begins digitizing the next analog signal in succession. In this manner, the pipelined analog-to-digital converter digitizes multiple analog signals, each in segments, starting with the most significant segment of the signal and proceeding through the pipeline stages until the least significant bit (or bits) is digitized by the last stage. The general goal of pipelined conversion is to provide a high throughput while adding latency.
FIG. 1 illustrates a conventional pipelined analog-to-digital design used in some commercial products. As shown, a pipelined analog-to-digital converter includes multiple stages (M different stages in this example). An analog signal 12 (Vin) is provided to a first stage 14 which quantizes a portion of analog signal 12 B bits in length. As mentioned, the most significant bits of analog signal 12 are quantized (digitized) by first stage 14. Stage 14 then outputs the unquantized least significant portion of the analog signal to the next successive stage. That stage then quantizes the next most significant B bits of the signal and outputs the residue to the next successive stage (if any). Eventually, the residue of a nearly completely quantized analog signal reaches the next to last stage 16 where the next to least significant B bits are quantized. Stage 16 then outputs the final unquantized residue of the analog signal to a final stage 18 which quantizes the least significant B bits of the signal. At this point, the entire analog signal 12 has been digitized in M separate B bit segments. Each of these B bit segments of digitized signal are assembled to provided the final digitized value of analog input signal 12.
It should be understood that there is no requirement that each of the M stages in pipelined converter 10 quantizes exactly B bits. Some stages may quantize more bits than others. In the lower portion of FIG. 1, an exemplary design for first stage 14 is illustrated. As shown, the input to stage 14 is unconverted analog signal 12 and the output from stage 14 is a residue 15 of analog signal 12 which does not include the most significant bits of the digitized signal.
Within stage 14, a sample and hold amplifier 20 holds the input sample for a defined period of time to allow subsequent comparison. The analog signal output the amplifier 20 is provided to both a coarse analog-to-digital converter 22 and to an adder 24. Analog-to-digital converter 22 then digitizes the most significant B bits of the analog signal provided by amplifier 20. In one specific example, analog-to-digital converter 22 is a flash type analog-to-digital converter. Regardless of the actual design, A/D converter 22 should have a resolution of B bits. The B bits of digitized signal are then output as a digital signal 26. Digital signal 26 is also fed to a digital-to-analog converter 28 which precisely reconverts the most significant B bits back to an analog signal which is provided to adder 24 as a negative quantity. Thus, adder 24 subtracts the value of the most significant portion of analog signal 12 from the entire analog signal 12 (which was provided directly from amplifier 20). The result is a residue analog signal 32 which is provided to an interstage amplifier 34. Amplifier 34 multiplies residue signal 32 by 2 to the B power. This shifts the value of the analog residue ahead by B bits. Thus, the second most significant B bits are advanced to the magnitude of the most significant bits in analog residue signal 15. The shifted and amplified residue signal 15 is then handed off to the second stage where it undergoes a similar operation to digitize the second most significant B bits and output a residue lacking the 2*B most significant bits. Note that if digital error correction is implemented, amplifier 34 multiplies residue 32 by 2.sup.(B-1), not 2.sup.B.
Various stages in the pipelined design have different demands and therefore need not be identically designed (see T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter," IEEE Journal of Solid-State Circuits, Vol. 30, No. 3, (1995) which is incorporated herein by reference in its entirety and for all purposes). This is because with each successive stage, the analog output signal has to settle at a precision that scales with 2.sup.(B*d) --where d is the depth of the pipeline at the current stage--thereby relaxing the speed requirements for the later stages.
This invention relates to detector arrays including pipelined analog-to-digital converters (preferably on a single chip). When a pipeline design (like any other analog-to-digital converter design) is applied to a large array of detectors such as photodiodes in a CMOS imager, optimization requires fundamental tradeoffs between converter speed, pitch constraints, and power dissipation. At the one extreme, a single analog-to-digital converter could be provided for every pixel or every row of pixels. In such case, the converter can operate at a relatively slow rate; at the frame rate of a video recorder or the frame rate times a multiplier given by the number of pixels in a row. Often though pitch constraints make this solution unattractive; e.g., for a CMOS photosensor, the pitch is usually in the 4 to 10 micrometer range. Further, power dissipation scales linearly with the number of pixels, so numerous analog-to-digital converters collectively dissipate significant power around the chip's periphery. Still further, such designs can suffer from line routing difficulties, crosstalk, fixed pattern noise, and other problems associated with transmitting many signals to many separate analog-to-digital converters.
At the other extreme, a single analog-to-digital converter could be employed to digitize the outputs of all the pixels on the imager array. This architecture has the advantage of occupying less area on the chip's surface. However, it cannot be scaled up easily. It must operate very fast; at the frame rate times the total number of pixels on the imager. In the case of super VGA, with one million pixels for example, this means that the converter must operate at 30 MHz. Digital cameras have even more pixels and must operate even faster. Converters operating at these speeds can be difficult to design. Also, they can dissipate very large amounts of power concentrated at one location on the chip. This sets up large temperature gradients which can very detrimentally affect the quality of any image generated by the detector array. Another difficulty of designs employing only one or a few analog-to-digital converters is the requirement that an analog multiplexer be placed before the analog-to-digital converter. This multiplexer may introduce some errors into the analog signal presented to the converter.
Various intermediate solutions are available in which the number of separate analog-to-digital converters, the speed of the converters, the precisions of the converters, and the concentration of power dissipation are traded off. However, these tradeoffs become very severe when the number of input analog signals becomes large (in the case of digital camera detector for example). It is clear from this and the above discussion that improved analog digital converter architectures and associated integrated circuit designs would be welcome.